1. Technical Field
The present invention relates generally to an improved integrated circuit chip. More specifically, the present invention is directed to a high speed on-chip serial link apparatus and method.
2. Description of Related Art
State-of-the-art very large scale integrated (VLSI) chips need asynchronous serial interfaces to load configuration data for power-on reset, manufacturing test, debugging, and the like. These interfaces typically operate at very low clock frequencies compared to the system clocks and have clock ratios on the order of 100 to 10000 times slower than the system clock cycle, depending on the chosen implementation. These low clock frequencies result in slow power-on sequences, long manufacturing test cycles per chip, and long delays to transfer debug information during the chip “bring-up” phase.
In recent years, more and more stand-alone chips with separate asynchronous serial interfaces are integrated into complex systems-on-a-chip using the latest VLSI technologies. The known solution to this integration problem is to replicate the asynchronous serial interfaces for each unit including the synchronization logic and the complete decoder. This replication results in a large overhead with regard to silicon area and an additional clock distribution network.
Two known solutions for the physical interconnection of these interfaces on the chip exist. In a first solution, a serial clock, with a frequency much lower than the system cycle frequency, is distributed to the asynchronous serial interfaces. From a timing perspective with a physical design correlation, these clocks of the asynchronous interface can be treated as non-critical “don't care” (DC) signals.
In a second solution, the asynchronous serial interfaces are implemented with the maximum clock frequency according to the external component specification used. This requires that a complete new balanced clock tree be designed.
The first approach significantly reduces the system's performance due to the low frequency serial clock. With the second approach, significantly more design effort must be spent because of the added complexity to the physical design (additional clock domain and timed data signals).